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 Data Sheet PD No.60238
IRS2153D(S)PbF
SELF-OSCILLATING HALF-BRIDGE DRIVER IC
Features
Integrated 600V Half-Bridge Gate Driver CT, RT programmable oscillator 15.4V Zener Clamp on VCC Micropower Startup Non-latched shutdown on CT pin (1/6th VCC) Internal bootstrap FET Excellent Latch Immunity on All Inputs & Outputs +/- 50V/ns dV/dt immunity ESD Protection on All Pins 8-lead SOIC or PDIP package 1.1 usec (typ.) internal deadtime
Product Summary
VOFFSET Duty Cycle Driver source/sink current Vclamp Deadtime 600V Max 50% 180/260mA typ. 15.4V typ. 1.1us typ.
Description
The IRS2153D is based on the popular IR2153 selfoscillating half-bridge gate driver IC using a more advanced silicon platform, and incorporates a high voltage half-bridge gate driver with a front end oscillator similar to the industry standard CMOS 555 timer. HVIC and latch immune CMOS technologies enable rugged monolithic construction. The output driver features a high pulse current buffer stage designed for minimum driver cross-conduction. Noise immunity is achieved with low di/dt peak of the gate drivers.
Package
PDIP8 IRS2153DPBF
SO8 IRS2153DSPBF
Typical Connection Diagram
+ AC Rectified Line
RVCC
VCC
1
8
VB CBOOT MHS
IRS2153D
RT
2
7
HO
RT CT CVCC CT COM
3
6
VS
L
RL
4
5
LO
MLS
- AC Rectified Line
1
IRS2153D(S)PbF
Absolute Maximum Ratings
Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM, all currents are defined positive into any lead. The Thermal Resistance and Power Dissipation ratings are measured under board mounted and still air conditions.
Symbol
VB VS VHO VLO IRT VRT VCT ICC IOMAX dVS/dt PD PD RJA RJA TJ TS TL
Parameter Definition
High Side Floating Supply Voltage High Side Floating Supply Offset Voltage High-Side Floating Output Voltage Low-Side Output Voltage RT Pin Current RT Pin Voltage CT Pin Voltage Supply Current (Note 1) Maximum allowable current at LO and HO due to external power transistor Miller effect. Allowable Offset Voltage Slew Rate Maximum Power Dissipation @ TA +25C, 8-Pin DIP Maximum Power Dissipation @ TA +25C, 8-Pin SOIC Thermal Resistance, Junction to Ambient, 8-Pin DIP Thermal Resistance, Junction to Ambient, 8-Pin SOIC Junction Temperature Storage Temperature Lead Temperature (Soldering, 10 seconds)
Min.
-0.3 VB - 25 VS - 0.3 -0.3 -5 -0.3 -0.3 ---500 -50 ---------55 -55 ---
Max.
625 VB + 0.3 VB + 0.3 VCC + 0.3 5 VCC + 0.3 VCC + 0.3 20 500 50 1.0 0.625 85 128 150 150 300
Units
V V V V mA V V mA
V/ns W W C/W C/W C
Note 1: This IC contains a zener clamp structure between the chip VCC and COM which has a nominal breakdown voltage of 15.4V. Please note that this supply pin should not be driven by a DC, low impedance power source greater than the VCLAMP specified in the Electrical Characteristics section.
2
IRS2153D(S)PbF
Recommended Operating Conditions
For proper operation the device should be used within the recommended conditions.
Symbol
VBS VS VCC ICC TJ
Parameter Definition
High Side Floating Supply Voltage Steady State High Side Floating Supply Offset Voltage Supply Voltage Supply Current Junction Temperature
Min.
VCC - 0.7 -3.0 (Note 2) VCCUV+ +0.1V (Note 3) -40
Max.
VCLAMP 600 VCC CLAMP 5 125
Units
V V V mA C
Note 2: Care should be taken to avoid output switching conditions where the VS node flies inductively below ground by more than 5V. Note 3: Enough current should be supplied to the VCC pin of the IC to keep the internal 15.6V zener diode clamping the voltage at this pin.
Recommended Component Values
Symbol
RT CT
Parameter Component
Timing Resistor Value CT Pin Capacitor Value
Min.
1 330
Max.
-----
Units
k pF
IRS2153D Frequency vs. RT
Frequency (Hz) 1000000 CT Values 100000 10000 1000 100 10 1000 10000 100000 1000000 RT (Ohm) 330pf 470pF 1nF 2.2nF 4.7nF 10nF
3
IRS2153D(S)PbF
Electrical Characteristics
VBIAS (VCC, VBS) = 14V, CT = 1 nF, VS=0V and TA = 25C unless otherwise specified. The output voltage and current (VO and IO) parameters are referenced to COM and are applicable to the respective output leads: HO or LO.
Symbol
VCCUV+ VCCUVVCCUVHYS IQCCUV IQCC ICC VCC CLAMP IQBS VBSUV+ VBSUVILK fOSC d ICT ICTUV VCT+ VCTVCTSD VRT+ VRTVRTUV VRTSD
Definition
Rising VCC Undervoltage Lockout Threshold Falling VCC Undervoltage Lockout Threshold VCC Undervoltage Lockout Hysteresis Micropower Startup VCC Supply Current Quiescent VCC Supply Current VCC Supply Current VCC Zener Clamp Voltage Quiescent VBS Supply Current VBS Supply Undervoltage Positive Going Threshold VBS Supply Undervoltage negative Going Threshold Offset Supply Leakage Current Oscillator Frequency RT Pin Duty Cycle CT Pin Current UV-Mode CT Pin Pulldown Current Upper CT Ramp Voltage Threshold Lower CT Ramp Voltage Threshold CT Voltage Shutdown Threshold High-Level RT Output Voltage, VCC - VRT Low-Level RT Output Voltage UV-Mode RT Output Voltage SD-Mode RT Output Voltage, VCC - VRT
Min
10.2 8.3 1.6 ------14.4 --8.0 7.0 --18.4 88 ----0.20 ----2.2 ---------------
Typ
10.8 8.8 2.0 130 800 1.8 15.4 60 9.0 8.0 --19.0 93 50
0.02
Max
11.5 9.4 2.4 170 1000 --16.8 80 9.5 9.0 50 19.6 100 --1.0 0.6 ----2.4 50 300 50 300 100 50 300
Units
Test Conditions
Low Voltage Supply Characteristics V A A mA V A V RT = 36.9k ICC = 5mA VCC VCCUV-
Floating Supply Characteristics
A kHz % A mA V mV mV mV mV mV mV mV
VB = VS = 600V RT = 36.5k RT = 7.15k
fo < 100kHz VCC = 7V
Oscillator I/O Characteristics
0.30 9.32 4.66 2.3 10 100 10 100 0 10 100
IRT = -100A IRT = -1mA IRT = 100A IRT = 1mA VCC VCCUVIRT = -100A,
VCT = 0V
IRT = -1mA,
VCT = 0V
4
IRS2153D(S)PbF
Electrical Characteristics
VBIAS (VCC, VBS) = 14V, CT = 1 nF, VS=0V and TA = 25C unless otherwise specified. The output voltage and current (VO and IO) parameters are referenced to COM and are applicable to the respective output leads: HO or LO.
Symbol
VOH VOL VOL_UV tr tf tsd td IO+ IO-
Definition
High-Level Output Voltage Low-Level Output Voltage UV-Mode Output Voltage Output Rise Time Output Fall Time Shutdown Propagation Delay Output Deadtime (HO or LO) Output source current Output sink current
Min
------------0.65 -----
Typ
VCC COM COM 120 50 350 1.1 180 260
Max
------220 80 --1.75 -----
Units
Test Conditions
Gate Driver Output Characteristics IO = 0A IO = 0A IO = 0A, VCC VCCUV-
nsec
sec mA
Bootstrap FET Characteristics VB_ON IB_CAP IB_10V VB when the bootstrap FET is on VB source current when FET is on VB source current when FET is on --40 10 13.7 55 12 ------V mA
CBS=0.1uF VB=10V
5
IRS2153D(S)PbF
Lead Definitions
VCC
1
8
VB
RT
IRS2153D
2
7
HO
CT
3
6
VS
COM
4
5
LO
Symbol
VCC RT CT COM LO VS HO VB Oscillator timing resistor input Oscillator timing capacitor input IC power and signal ground Low-side gate driver output High voltage floating supply return High-side gate driver output High side gate driver floating supply
Lead Description
Logic and internal gate drive supply voltage
Functional Block Diagram
RT 2 R + R R + R/2 SQ R1 R2 S Q Q
DEAD TIME DEAD TIME PULSE
HV LEVEL SHIFT
8
VB
Q PULSE FILTER R S
6
BOOTSTRAP DRIVE
7
HO
VS
GEN
15.4V
1 VCC
CT 3 R/2
+ -
DELAY
5
LO
4
COM
M1
UV DETECT
6
IRS2153D(S)PbF
Timing Diagram
Operating Mode
VCCUV+
VCC
Fault Mode: CT <1/6*VCC
2/3 VCC
VCT
1/3 VCC 1/6 VCC
VCC
LO
VCC
DT
HO
DT
VCC
VRT
IRT
Switching Time Waveform
Deadtime Waverform
90%
tr 90%
tf
LO
DTLO
10%
DTHO
HO
90%
HO LO
10%
10%
7
IRS2153D(S)PbF
Functional Description
Under-voltage Lock-Out Mode (UVLO)
The under-voltage lockout mode (UVLO) is defined as the state the IC is in when VCC is below the turn-on threshold of the IC. The IRS2153D under voltage lock-out is designed to maintain an ultra low supply current of less than 155uA, and to guarantee the IC is fully functional before the high and low side output drivers are activated. During under voltage lock-out mode, the high and low-side driver outputs HO and LO are both low.
Bootstrap MOSFET
The internal bootstrap FET and supply capacitor (CBOOT) comprise the supply voltage for the high side driver circuitry. The internal boostrap FET only turns on when LO is high. To guarantee that the high-side supply is charged up before the first pulse on pin HO, the first pulse from the output drivers comes from the LO pin.
Normal operating mode
Once the VCCUV+ threshold is passed, the MOSFET M1 opens, RT increases to approximately VCC (VCC-VRT+) and the external CT capacitor starts charging. Once the CT voltage reaches VCT- (about 1/3 of VCC), established by an internal resistor ladder, LO turns on with a delay equivalent to the deadtime td. Once the CT voltage reaches VCT+ (approximately 2/3 of VCC), LO goes low, RT goes down to approximately ground (VRT-), the CT capacitor discharges and the deadtime circuit is activated. At the end of the deadtime, HO goes high. Once the CT voltage reaches VCT-, HO goes low, RT goes high again, the deadtime is activated. At the end of the deadtime, LO goes high and the cycle starts over again. The following equation provides the oscillator frequency:
Supply voltage
+ AC Rectified Line RVCC
VCC
1
8
VB CBOOT MHS
RT
IRS2153D
2
7
HO
RT CT CVCC CT COM
3
6
VS
L
RL
4
5
LO
MLS
f~
1 1.453 x RT x CT
- AC Rectified Line
Fig. 1 Typical Connection Diagram Fig. 1 shows an example of supply voltage. The start-up capacitor (CVCC) is charged by current through supply resistor (RVCC) minus the start-up current drawn by the IC. This resistor is chosen to provide sufficient current to supply the IRS2153D from the DC bus. CVCC should be large enough to hold the voltage at Vcc above the UVLO threshold for one half cycle of the line voltage as it will only be charged at the peak, typically 0.1uF. It will be necessary for RVCC to dissipate around 1W. The use of a two diode charge pump made of DC1, DC2 and CVS (Fig. 2) from the half bridge (VS) is also possible however the above approach is simplest and the dissipation in RVCC should not be unacceptably high.
+ AC Rectified Line
This equation can vary slightly from actual measurements due to internal comparator over- and under-shoot delays. For a more accurate determination of the output frequency, the frequency characteristic curves should be used (RT vs. Frequency, Page 3).
Shut-down
If CT is pulled down below VCTSD (approximately 1/6 of VCC) by an external circuit, CT doesn't charge up and oscillation stops. LO is held low and the bootstrap FET is off. Oscillation will resume once CT is able to charge up again to VCT-.
RVCC
VCC
1
8
VB CBOOT MHS DC2 VS CVS L
IRS2153D
RT
2
7
HO
RT CT CVCC CT COM
3
6
RL
4
5
LO
MLS DC1
- AC Rectified Line
Fig. 2 Charge pump circuit The supply resistor (RVCC) must be selected such that enough supply current is available over all operating conditions. Once the capacitor voltage on VCC reaches the start-up threshold VCCUV+, the IC turns on and HO and LO begin to oscillate.
8
IRS2153D(S)PbF
19
100 98 Frequency (kHz) 96 94 92
18.8 Frequency (kHz)
18.6
18.4
18.2
18 11 12 13 VCC(V) 14 15 16
90 -25
0
25
50
75
100
125
Temperature(C)
FREQ vs VCC
FREQ vs TEMP
1.25
1.4
1.3
1.15
DT(uS)
1.1
DT(uS)
1.2
1.05
0.95
1
0.85
0.9 11 12 13 VCC(V) 14 15 16
0.75 -25
0
25
50
75
100
125
Temperature(C)
DT vs VCC
17
DT vs TEMP
90 80 70
Temperature(C)
60 50 40 30 20 10 0 20 70 120 Frequency(kHz)
VCC (V)
16
15 -25 0 25 50 75 100 125
Temperature (C) VCC CLAMP vs TEMP
Tj vs. Frequency (SOIC)
9
IRS2153D(S)PbF
300 250 HOCurrent (mA) 200 150 100 50 0 -25 300
IsinkHO
LO Current (mA)
250 200 150 100 50 0 -25
IsinkHO
IsourceHO
IsourceLO
0
25
50
75
100
125
0
25
50
75
100
125
Temperature(C)
Temperature(C)
IsourceHO,IsinkHO vs Temp
IsourceLO,IsinkLO vs Temp
80 70 IB_CAP, IBS_10V (mA) 60 50 40 30 20 10 0 -25 IBS_10V IB_CAP
0
25
50
75
100
125
Temperature(C)
IBCAP, IBS10V vs TEMP
10
IRS2153D(S)PbF
IRS2153DSPbF
IRS2153DPbF
12
IRS2153D(S)PbF
ORDER INFORMATION
Leadfree Part 8-Lead PDIP IRS2153D order IRS2153DPbF 8-Lead SOIC IRS2153DS order IRS2153DSPbF
WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, Tel: (310) 726 8000 Sales Offices, Agents and Distributors in Major Cities Throughout the World. Data and specifications subject to change without notice.
Qualification: Industrial, MSL2 Leadfree
(c) 2005 International Rectifier 10-15-2005
http://www.irf.com 11


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